Array substrate and method of manufacturing the same
US7759738B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Nov 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136295
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.