Microelectronic package with wear resistant coating
US7759780B2 · kind B2 · utility
0Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Sep 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.