Timing adjustment circuit
US7759998B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 29, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide with one another. If all the output data coincide with one another, the latch timing is maintained, whereas if the output data of the flip-flop latching the data signal at a fastest or latest timing differs from the output data of the flip-flop latching the data signal at the central timing, the judging circuit changes the variable timing to obtain a suitable latch timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.