Low voltage analog CMOS switch
US7760007B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Dec 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS analog switch circuit includes an NMOS switch transistor, a PMOS switch transistor, and a bias circuit. In an embodiment, the bias circuit includes a first and a second native bias transistors having their gate terminals coupled to a first and a second terminals of the CMOS switch circuit, respectively. The source terminals of the first and the second native bias transistors are coupled together and are also coupled to the body terminal of the PMOS switch transistor. In an configuration, the first and the second native bias transistors are characterized by substantially 0V threshold voltages, and the PMOS switch transistor is configured to exhibit a lower on-resistance in response to the greater of the voltages of the first terminal and the second terminal of the CMOS analog switch circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.