Low power serdes architecture using serial I/O burst gating
US7760115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Sep 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A serializer/deserializer is disclosed with a flexible design that allows for sending data streams between computer systems where the power dissipation is markedly reduced by placing the serializer/deserializer in a standby, low power mode between the sending of data. Word data bits are framed and sent along with clock pulses that define when the bits may be reliably received. High speed, typically, CML logic is used for the transmission line drivers and together with the clock pulse, a data word is sent faster than the computer system can send the next word to the serializer/deserializer. The disclosure frames the word and detects the word end, whereupon the system is placed into the standby mode. In addition the serializer/deserializers may be placed in a master/slave arrangement where the slave can be arranged to use the master's clock to send word data bits back to the master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.