Technique for combining in-rush current limiting and short circuit current limiting
US7760479B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jun 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/0822
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A circuit that protects from high power-on in-rush currents and short circuits. The circuit has a pass transistor and a parallel smaller transistor. A comparator senses when an output voltage crosses a reference and turns off the pass transistor and turns on the parallel smaller transistor. The parallel smaller transistor has a higher “on” resistance so that the short circuit or the in-rush current does not harm the electronics. When the short circuit or in-rush current condition is removed, the comparator senses this condition and returns to the normal operation where the pass transistor is on and the parallel small transistor is off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.