Patent · US Active

Programmable power down scheme for embedded memory block

US7760577B1 · kind B1 · utility

1Cited by

1References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Wei Yee Koay · Kampung Bukit Kechil, MY
Teng Chow Ooi · Bayan Lepas, MY
Ngee Kiat Chieng · Kulim, MY
Yau Kok Lai · Bukit Mertajam, MY
Mei Ching Lim · Mantin, MY

Key dates

Filing date	Sep 18, 2008
Grant date	Jul 20, 2010
Priority date	—
Expiry date	Jan 20, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2227
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated circuit configured to selectively provide power to used portions of a memory array is presented. The integrated circuit includes an array of memory cells for storing digital data and a power bus interconnecting structure. The power bus interconnecting structure includes global power buses in communication with local power buses through programmable vias. The array of memory cells are remapped so that unused column portions of the memory array become unused row portions of the memory array. The programmable vias are selectively located during design of the integrated circuit, providing power to the used portions of the memory array.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.