Efficient use of a render cache
US7760804B2 · kind B2 · utility
6Cited by
10References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2004 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | May 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Image data is processed into first and second component pixel blocks, where each of the first blocks is associated with a respective one of the second blocks to define a combination pixel block. The first and second blocks are written to memory through a cache that is used as a write buffer. The cache is logically partitioned into a contiguous portion to store the first blocks and not any second blocks, and another contiguous portion to store the second blocks and not any first blocks. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.