High frequency divider state correction circuit
US7760843B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Aug 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.