Decoder architecture system and method
US7760880B2 · kind B2 · utility
8Cited by
3References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2005 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1137
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decoder may perform node data reordering for bit node processing and node data reordering for bit node to check node interconnections. The decoder may also utilize a single barrel shifting operation on data read from an edge memory for bit node processing or check node processing during a memory read operation. The decoder may also utilize a single format conversion on data read from an edge memory for bit node processing or check node processing. The decoder may also utilize a simplified check node process for check node processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.