Addressable serial peripheral interface
US7761633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2008 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Jan 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressable SPI bus and an associated communication protocol. The addressable SPI bus comprises a plurality of slaves each exhibiting a particular address and a shift register whose output is connected to a common MISO bus by a buffer exhibiting a three state output, also known as a tri-state output. The master asserts a single SS line, which is connected in parallel to each of the plurality of slaves, indicating the beginning of a frame, and transmits via the MOSI bus the address of a particular slave of the plurality of slaves, denoted interchangeably the target or destination slave. Responsive to the received address, the target slave enables the three state output associated therewith thus transmitting the output of the target slave shift register to the master via the MISO bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.