Apparatus, system, and method for resetting an inter-integrated circuit data line with a clock line
US7761728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method are disclosed for resetting an inter-integrated circuit data line with a clock line. A hang module detects that a data line that carries data between an I2C bus master and an I2C bus slave is hung, wherein the I2C bus master and I2C bus slave communicate over the data line and a clock line that carries a clock signal. The clock module increases a clock line frequency to a specified frequency in response to the detected data line hang. The pulse generation module transmits specified clock pulses from the I2C bus master to the I2C bus slave over the clock line at the specified increased frequency in response to the detected data line hang. A frequency detector module detects clock pulses at the specified increased frequency. A timer module detects the specified clock pulses at the specified increased frequency. A reset module resets the I2C bus slave in response detecting the specified clock pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.