Debugging method
US7761744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Sep 9, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a debugging method applicable for an embedded system. The system includes a processor, a main memory and a debugging interface. A debugging program is first provided in the main memory. A debugging interruption is subsequently triggered to cause the processor to read the debugging program from the main memory and execute the debugging program. After execution, an execution result of the debugging program is stored into the main memory. The execution result is read and output via the debugging interface for further analysis. Because the architecture does not require a scan chain of ITR 104, the circuit requirement is reduced while performance is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.