Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method
US7761779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2006 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Mar 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.