Patent · US Active

System and method to generate an IC layout using simplified manufacturing rule

US7761824B2 · kind B2 · utility

6Cited by

4References

9Claims

0Family size

Inventors

Marko P. Chew · Cupertino, US
Yue Yang · Chengdu, CN

Key dates

Filing date	Jul 2, 2007
Grant date	Jul 20, 2010
Priority date	—
Expiry date	Sep 12, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/398
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments of the invention provide a system and method where a physical design (“PD”) process can use simplified manufacturing rules to generate an integrated circuit (“IC”) layout. A layout optimization process transforms the PD generated layout to become more manufacturing rule compliant layout using a full set of manufacturing rules. The invention increases the probability of the PD process successfully generates an IC layout since the PD is not burdened with having to consider the full complexity of the manufacturing rules.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.