Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions
US7761827B1 · kind B1 · utility
10Cited by
1References
18Claims
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Key dates
| Filing date | Aug 1, 2007 |
| Grant date | Jul 20, 2010 |
| Priority date | — |
| Expiry date | Dec 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a first input of the first logic element, due to a second input of the first logic element. To this end, at least one second logic element may be disabled based on the identified condition for power savings or other purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.