Pseudo low volume reticle (PLVR) design for ASIC manufacturing
US7763414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2008 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Oct 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/50
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A Pseudo Low Volume Reticle (PLVR) which consists of multiple design layers on a single reticle. Specifically, the reticle can include two instances of each layer in order to facilitate die-to-die inspection techniques. A scribe is wrapped around each instance of the layer, such that both the frame and active area of the chip can be inspected with the die-to-die method. The chip consists of design data for a given part. The scribe, or frame, is preferably standard data across products which is used for yield and in line testing during the chip manufacturing process. Since only one chip and scribe unit is necessary to manufacture a device at each layer, it is only necessary that one chip and scribe instance yield during the reticle manufacturing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.