Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement
US7763987B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Nov 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.