Buffer circuit, buffer tree, and semiconductor device
US7764085B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Sep 18, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN). The control circuit performs control so that when the input signal is at a second logic level corresponding to the second power supply, the second transistor is turned off, when the input signal goes to a first logic level corresponding to the first power supply, the second transistor is turned on to cause the output terminal (OUT) to a second power supply voltage, next, when the second transistor is turned off and then the input signal undergoes a transition from the first logic level to the second logic level and the first transistor switches from off to on, with the second transistor being kept off. A flip-flop is connected to the output te…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.