Voltage shift control circuit for PLL
US7764093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2004 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Dec 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/187
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL comprises a PFD, a loop filter and a VCO, as well as a voltage shift capacitor coupling the PFD and the VCO. A voltage shift control circuit is placed in parallel with the voltage shift capacitor. This circuit comprises controlled charging means, which are designed to charge the voltage shift capacitor according to a channel control signal. It also comprises controlled pre-charging means which are designed to accelerate the charging of the voltage shift capacitor by the controlled charging means. It further comprises controlled biasing means, designed to ensure the bias of the input during the pre-charging of the voltage shift capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.