Electrostatic discharge circuit and method for reducing input capacitance of semiconductor chip including same
US7764475B2 · kind B2 · utility
5Cited by
6References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | May 5, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A multi-mode electrostatic discharge (ESD) circuit for a semiconductor chip comprises first and second ESD diodes. In a first mode, a body voltage greater than a power source voltage of the semiconductor chip is applied to the first ESD diode and a body voltage less than a ground voltage of the semiconductor chip is applied to the second ESD diode. In a second mode, a body voltage substantially equal to the power source voltage of the semiconductor chip is applied to the body of the first ESD diode and a body voltage substantially equal to the ground voltage of the semiconductor chip is applied to the second ESD diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.