Low power, small size SRAM architecture
US7764535B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 2008 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Nov 10, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell for driving a complementary pair of electrodes associated with a micro-mirror of a spatial light modulator includes two PMOS transistors coupled to a voltage source providing a source voltage. The two PMOS transistors are characterized by a first size. The memory cell also includes two NMOS transistors coupled to ground. Each of the two NMOS transistors are coupled to one of the two PMOS transistors and are characterized by a second size substantially equal to the first size. The memory cell further includes two word line transistors coupled to a word line and characterized by a third size substantially equal to the first size. Power savings associated with the precharge circuit on the order of (Vdh/Vdl)2=36 are achieved in some embodiments.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.