Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory
US7764551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2008 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jan 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.