Linear sample and hold phase detector for clocking circuits
US7764759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2006 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal. The sample and hold circuit is coupled to the first and second phase difference output signals and samples the voltage levels thereof in response to a first transition of the input data signal and holds the sampled voltage levels until a second transition of the input data signal. Novel clocking circuits using the linear sample and hold phase detector, as well as other types of linear phase detectors, are also disclosed herein in…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.