Method and system for robust elastic FIFO (EFIFO) in a port bypass controller
US7765343B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2004 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Jun 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/357
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Certain embodiments of the invention may be found in a method and system for handling data in port bypass controllers for storage systems and may comprise receiving a data stream from a receive port bypass controller's port and buffering at least a portion of the received data stream in at least one EFIFO buffer integrated within the port bypass controller. A data rate or frequency of the received data stream may be changed by inserting at least one extended fill word in the buffered portion of the received data stream or by deleting at least one fill word from the received data stream buffered in the EFIFO buffer. The extended fill word may comprise a loop initialization primitive (LIP), a loop port bypass (LPB), a loop port enable (LPE), a not operation state (NOS), an offline state (OLS), a link reset response (LRR) and/or a link reset (LR).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.