Scalable parallel pipeline floating-point unit for vector processing
US7765386B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8061
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates FP results from operating on scalar components of the vector inputs dispatched from the scheduler. An arbiter and assembly unit arbitrates use of output section and assembles the FP results to write to the output section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.