Design method and system for minimizing blind via current loops
US7765504B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2007 |
| Grant date | Jul 27, 2010 |
| Priority date | — |
| Expiry date | Sep 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09636
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.