Poly crystalline silicon semiconductor device and method of fabricating the same
US7768010B2 · kind B2 · utility
8Cited by
1References
5Claims
0Family size
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Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jul 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/441
Abstract
Provided are a poly crystalline silicon semiconductor device and a method of fabricating the same. Portions of a silicon layer except for gates are removed to reduce a parasitic capacitance caused from the silicon layer existing on gate bus lines. The silicon layer exists under the gates only, thus the parasitic capacitance is reduced and the deterioration and the delay of signals are prevented. Accordingly, the poly crystalline silicon semiconductor device, such as a thin film transistor, has excellent electric characteristics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.