Semiconductor memory devices including a damascene wiring line
US7768128B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory devices include an integrated circuit substrate and a plurality of lower wiring lines on the substrate and extending in a first direction. An interlayer insulating layer is on the plurality of lower wiring lines. An upper damascene wiring line is in an upper portion of the interlayer insulating layer and extending in a second direction, different from the first direction, to extend over the plurality of lower wiring lines. The upper damascene wiring line has protruded regions extending therefrom in a direction different from the second direction, the protruded regions extending over respective underlying ones of the lower wiring lines. A first via extends through the interlayer insulating layer under a first of the protruded regions and connects the upper damascene wiring line to a corresponding underlying first one of the plurality of wiring lines. A second via extends through the interlayer insulating layer under a second of the protruded regions and connects the upper damascene wiring line to a corresponding underlying second one of the plurality of wiring lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.