Voltage tolerant floating N-well circuit
US7768299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00384
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.