Programmable logic device providing serial peripheral interfaces
US7768300B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2009 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jul 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17756
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable logic device (PLD) includes a slave port and a master port. The slave port can receive a configuration data bitstream and a slave clock signal from a master port of a first external device. The master port can provide the configuration data bitstream and a master clock signal from the PLD to a slave port of a second external device. An interface block in the PLD can pass the configuration data bitstream from the slave port through the PLD to the master port. In another embodiment, a PLD includes a slave serial peripheral interface (SPI) port and configuration memory. The slave SPI port can receive a configuration data bitstream and a slave clock signal from a master SPI port of an external device. The configuration memory stores the received bitstream for configuring the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.