Decoder circuit, decoding method, output circuit, electro-optical device, and electronic instrument
US7768316B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2009 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Feb 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.