Process variation tolerant sense amplifier flop design
US7768320B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Nov 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.