Output gain stage for a power amplifier
US7768350B2 · kind B2 · utility
35Cited by
21References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Dec 30, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/537
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes multiple gain stages to receive and amplify a differential input signal at different common mode voltages. The stages each may include a pair of linear NMOS gain transistors coupled to a primary coil of a given output transformer. One of the stages may include commonly coupled terminals coupled to a center tap of the primary coil of an output transformer of another stage, and a supply current provided to one of the stages is re-used for the other stage(s).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.