Integrated circuit memory elements
US7768818B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Oct 11, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.