Stacked semiconductor device
US7768867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.