Data packet switch and method of operating same
US7769003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/253
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.