High speed serial link output stage having self adaptation for various impairments
US7769057B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2008 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jan 21, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03885
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed serial link structure and method are provided, comprising a data driver and a replica driver structure, the replica driver structure comprising a replica driver, a calibration engine and a peak level detector. The calibration engine compares a peak level detector output to a reference value and responsively performs a data driver adjustment, wherein the data driver adjustment comprises at least one of a driver biasing adjustment, a driver intermediate stage bandwidth adjustment and a driver equalization setting adjustment. In some embodiments, the calibration engine incorporates a comparator and a digital state machine; in other embodiments, it incorporates an analog operational amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.