Full CMOS min-sum analog iterative decoders
US7769798B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Apr 27, 2004 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 3, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3905
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Analog iterative decoders are provided that are based on the so-called min-sum algorithm (also referred to as max-sum or max-product, Max-Log-MAP or BP-based decoding) and can be used to decode powerful coding schemes such as low-density parity-check (LDPC) codes and turbo codes. The circuits can be implemented by standard CMOS technology, which means lower fabrication cost and/or simpler design compared to previously reported analog iterative decoders that are based on BiCMOS or sub-threshold CMOS technology. Soft information is passed among variable nodes and parity-check nodes. A low-voltage high-swing Max WTA circuit is also provided. The circuit can be implemented by short channel MOSFET transistors and yet provide a reasonably high degree of accuracy. Applications include soft computing, and analog signal processing, in general. A Min WTA circuit can also be built based on this circuit by subtracting the input currents from a large reference current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.