Partial-write-collector algorithm for multi level cell (MLC) flash
US7769944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Feb 20, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory system includes a multi level cell (MLC) flash memory organized into blocks and having pages of information, which has data and spare. The MLC flash memory includes at least a temporary area to store at least a portion of a page of information during a partial write operation. The MLC flash memory stores a page of information into a block identified by a target physical address. The flash memory system further includes a flash card micro-controller causes communication between a host flash card controller and the MLC flash memory and includes a buffer memory configured to store a portion of a page of information, where the micro-controller writes the at least a portion of a page of information to the temporary area and later copies the written at least a portion of a page of information into the block identified by a target physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.