Cached memory system and cache controller for embedded digital signal processor
US7769950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2004 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Mar 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cached memory system that can handle high-rate input data and ensure that an embedded DSP can meet real-time constraints is described. The cached memory system includes a cache memory located close to a processor core, an on-chip memory at the next higher memory level, and an external main memory at the topmost memory level. A cache controller handles paging of instructions and data between the cache memory and the on-chip memory for cache misses. A direct memory exchange (DME) controller handles user-controlled paging between the on-chip memory and the external memory. A user/programmer can arrange to have the instructions and data required by the processor core to be present in the on-chip memory well in advance of when they are actually needed by the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.