Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code
US7770050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Oct 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is translated to generate translated code instructions that emulate a second component of the target system on the host system. The interpreted instructions, are executed based on a first clock (which may be a fixed clock) and the translated instructions are executed based on a second clock (which may be a variable clock). The host system adjusts the first or second clock, execution of the translated or interpreted instructions or a memory access to maintain a desired synchronization between the translated instructions and the interpreted instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.