Serial concatenated convolutional code decoder
US7770087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2007 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Jun 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0055
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial concatenated convolutional code (SCCC) decoder is provided. The SCCC decoder is comprised of an input buffer memory (102), one or more processing loop modules (120), and an output buffer memory (112). Each processing loop module is comprised of a permutation module (110), an inner decoder module (104), a depermutation module (106), and an outer decoder module (108). The inner decoder module is subdivided into two (2) or more inner decoding engines (2021-202N) configured for concurrently performing a decoding operation based on an inner convolutional code. The outer decoder module is subdivided into two (2) or more outer decoding engines (4021-402N) configured for concurrently performing a decoding operation based on an outer convolutional code. The inner convolutional code and the outer convolutional code are designed in accordance with a maximum aposteriori probability based decoding algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.