Efficient decoders for LDPC codes
US7770090B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2005 |
| Grant date | Aug 3, 2010 |
| Priority date | — |
| Expiry date | Apr 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An LDPC decoder, applicable to LDPC codes including codes where check nodes within the same group are connected to a common bit node, successively processes groups of check nodes in a particular iteration, including updating bit nodes in that same iteration responsive to messages generated in response to processing a group of check nodes. Within an iteration, the LDPC decoder may also track the number of unresolved parity check equations, and cease iterating or output to an outer block decoder if that number reaches a local minima or standard minimum, falls below a predetermined threshold, or its rate of change falls below a predetermined threshold, indicating a lack of convergence or false convergence condition. The LDPC decoder may also provide a feedback assist to a demodulator. Also, a novel memory configuration may store messages generated by the decoder in the course of check node processing. The decoder may also employ a novel method for generating check node to bit node messages through a prescribed series of pair-wise computations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.