Semiconductor integrated circuit device and dummy pattern arrangement method
US7772070B2 · kind B2 · utility
11Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Feb 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A semiconductor integrated circuit device according to an embodiment of the present invention includes a functional circuit region including a functional circuit, a dummy region formed in a region other than the functional circuit region, and plural dummy MOSFETs formed in a dummy region and having a dummy gate electrode on a dummy diffusion layer, the plural dummy MOSFETs being arranged such that date rates of the dummy diffusion layer and dummy gate electrode are kept constant in a predetermined section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.