Hard mask arrangement, contact arrangement and methods of patterning a substrate and manufacturing a contact arrangement
US7772126B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Nov 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interlayer is disposed on a pattern surface of a substrate. A buried hard mask may be provided on the interlayer. The buried hard mask includes a template opening having a template length along a line axis and a template width perpendicular thereto. The buried hard mask is filled with a fill material. A top mask is provided above the filled buried hard mask. The top mask includes a trim opening crossing the template opening and having a trim width along the line axis that is smaller than the template length. By etching the fill material and the interlayer using the top and buried hard mask a process section of the pattern surface may be exposed such that a target length and width of the process section result from the template and the trim widths. The planar dimensions of the process section may be decoupled from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.