Semiconductor storage device comprising MIS transistor including charge storage layer
US7772618B2 · kind B2 · utility
3Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Oct 8, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell block. The memory cell block includes a plurality of n-type first MIS transistors with current passages connected in series. Each of the first MIS transistors includes a source, a drain, and a charge storage layer formed on a (001)-plane of a semiconductor substrate with a gate insulating film interposed therebetween and is configured to store data. A direction from the source to the drain in each of the first MIS transistors is set parallel to a [001]-direction or [010]-direction of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.