Output buffer circuit, differential output buffer circuit, output buffer circuit having regulation circuit and regulation function, and transmission method
US7772877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2008 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Dec 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/028
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.