Level shift circuit and method thereof
US7772912B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Nov 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shift circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a level shifter and an equalization unit. The first and second input terminals receive an input signal and an inverted input signal respectively. The first and second output terminals output an output signal and an inverted output signal respectively. The level shifter is connected to the first and second input terminals, the first and the second output terminals. The equalization unit is coupled between the first and second output terminals. Wherein, at a reset phase, the input signal and the inverted input signal are inputted to the level shifter, and the equalization unit is turned on. After the reset phase, the equalization unit is turned off and the level shifter starts to shift a level of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.