Frame-based phase-locked display controller and method thereof
US7773153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2005 |
| Grant date | Aug 10, 2010 |
| Priority date | — |
| Expiry date | Jun 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A frame-based phase-locked display controller used in a display system and method thereof are described. The frame-based phase-locked display controller for displaying a plurality of image frames in a video signal comprises a frame-based phase-locked loop and a synchronization signal generator. The frame-based phase-locked loop receives an oscillating signal and an input vertical synchronous signal to generate an output clock signal by phase-lock loop based on the frames. The synchronization signal generator, coupled to the frame-based phase-locked loop, receives the output clock signal to generate an output horizontal synchronous signal, an output vertical synchronous signal and an output display enable (DE) signal. The frame-based phase-locked loop comprises a first PLL, a frequency synthesizer, a second PLL, a fast phase detector, a phase frequency detector and an active pixel region generator. The active pixel region generator receives an input vertical synchronous signal to generate a reference signal associated with an active pixel region. The frame-based phase-locked loop frame-based phase-locks the display enable signal to the reference signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.